Running: ./testmodel.py --libraries=/home/hudson/saved_omc/libraries/.openmodelica/libraries/ --ompython_omhome=/usr Modelica_4.0.0_Modelica.Electrical.Digital.Examples.DFFREGSRL.conf.json loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo", uses=false) loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo", uses=false) loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 4.0.0+maint.om/package.mo", uses=false) Using package Modelica with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 4.0.0+maint.om/package.mo) Using package Complex with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo) Using package ModelicaServices with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo) Running command: translateModel(Modelica.Electrical.Digital.Examples.DFFREGSRL,tolerance=1e-06,outputFormat="mat",numberOfIntervals=5000,variableFilter="time|dFFREGSRL.dataOut.1.|dFFREGSRL.dataOut.2.",fileNamePrefix="Modelica_4.0.0_Modelica.Electrical.Digital.Examples.DFFREGSRL") translateModel(Modelica.Electrical.Digital.Examples.DFFREGSRL,tolerance=1e-06,outputFormat="mat",numberOfIntervals=5000,variableFilter="time|dFFREGSRL.dataOut.1.|dFFREGSRL.dataOut.2.",fileNamePrefix="Modelica_4.0.0_Modelica.Electrical.Digital.Examples.DFFREGSRL") Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo): time 0.001154/0.001154, allocations: 105.6 kB / 17.69 MB, free: 5.523 MB / 14.72 MB Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo): time 0.001174/0.001174, allocations: 192.7 kB / 18.63 MB, free: 4.594 MB / 14.72 MB Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 4.0.0+maint.om/package.mo): time 1.231/1.231, allocations: 222.9 MB / 242.3 MB, free: 15.17 MB / 206.1 MB Notification: Performance of FrontEnd - Absyn->SCode: time 1.988e-05/1.989e-05, allocations: 2.281 kB / 302 MB, free: 5.219 MB / 238.1 MB Notification: Performance of NFInst.instantiate(Modelica.Electrical.Digital.Examples.DFFREGSRL): time 0.002642/0.002674, allocations: 1.798 MB / 303.8 MB, free: 3.422 MB / 238.1 MB Notification: Performance of NFInst.instExpressions: time 0.002083/0.00477, allocations: 1.05 MB / 304.9 MB, free: 2.371 MB / 238.1 MB Notification: Performance of NFInst.updateImplicitVariability: time 7.27e-05/0.004856, allocations: 4 kB / 304.9 MB, free: 2.367 MB / 238.1 MB Notification: Performance of NFTyping.typeComponents: time 0.0001322/0.004994, allocations: 31.72 kB / 304.9 MB, free: 2.336 MB / 238.1 MB Notification: Performance of NFTyping.typeBindings: time 0.0002274/0.005228, allocations: 171.5 kB / 305.1 MB, free: 2.168 MB / 238.1 MB Notification: Performance of NFTyping.typeClassSections: time 0.0002773/0.005524, allocations: 143.7 kB / 305.2 MB, free: 2.027 MB / 238.1 MB Notification: Performance of NFFlatten.flatten: time 0.0006116/0.006145, allocations: 0.6608 MB / 305.9 MB, free: 1.367 MB / 238.1 MB Notification: Performance of NFFlatten.resolveConnections: time 0.0001609/0.006315, allocations: 94.17 kB / 306 MB, free: 1.277 MB / 238.1 MB Notification: Performance of NFEvalConstants.evaluate: time 0.001068/0.00739, allocations: 1.217 MB / 307.2 MB, free: 60 kB / 238.1 MB Notification: Performance of NFSimplifyModel.simplify: time 0.0002034/0.007603, allocations: 179.4 kB / 307.3 MB, free: 15.88 MB / 254.1 MB Notification: Performance of NFPackage.collectConstants: time 7.911e-05/0.00769, allocations: 36 kB / 307.4 MB, free: 15.85 MB / 254.1 MB Notification: Performance of NFFlatten.collectFunctions: time 7.129e-05/0.007768, allocations: 40 kB / 307.4 MB, free: 15.81 MB / 254.1 MB Notification: Performance of combineBinaries: time 0.0003802/0.008155, allocations: 428.1 kB / 307.8 MB, free: 15.39 MB / 254.1 MB Notification: Performance of replaceArrayConstructors: time 0.0001089/0.008271, allocations: 193.2 kB / 308 MB, free: 15.2 MB / 254.1 MB Notification: Performance of NFVerifyModel.verify: time 9.125e-05/0.008368, allocations: 55.94 kB / 308.1 MB, free: 15.14 MB / 254.1 MB Notification: Performance of FrontEnd: time 2.761e-05/0.008401, allocations: 11.88 kB / 308.1 MB, free: 15.13 MB / 254.1 MB Notification: Model statistics after passing the front-end and creating the data structures used by the back-end: * Number of equations: 43 (22) * Number of variables: 43 (28) Notification: Performance of Bindings: time 0.001206/0.009612, allocations: 1.337 MB / 309.4 MB, free: 13.68 MB / 254.1 MB Notification: Performance of FunctionAlias: time 0.0001681/0.009787, allocations: 135.8 kB / 309.6 MB, free: 13.55 MB / 254.1 MB Notification: Performance of Early Inline: time 0.001035/0.01083, allocations: 1.113 MB / 310.7 MB, free: 12.41 MB / 254.1 MB Notification: Performance of simplify1: time 1.194e-05/0.01085, allocations: 8 kB / 310.7 MB, free: 12.4 MB / 254.1 MB Notification: Performance of Alias: time 0.0008448/0.0117, allocations: 0.7599 MB / 311.4 MB, free: 11.58 MB / 254.1 MB Notification: Performance of simplify2: time 8.286e-06/0.01172, allocations: 7.969 kB / 311.4 MB, free: 11.57 MB / 254.1 MB Notification: Performance of Events: time 0.0008094/0.01253, allocations: 0.7475 MB / 312.2 MB, free: 10.74 MB / 254.1 MB Notification: Performance of Detect States: time 0.0004854/0.01303, allocations: 491.7 kB / 312.7 MB, free: 10.24 MB / 254.1 MB Notification: Performance of Partitioning: time 0.0003186/0.01335, allocations: 287.9 kB / 313 MB, free: 9.953 MB / 254.1 MB Error: Internal error NBResolveSingularities.noIndexReduction failed. (2|2) Unmatched Variables *************************** [DISC] (1) protected Integer dFFREGSRL.dFFSR.clock_flag (start = 0) slice: {} [DISC] (1) protected Integer dFFREGSRL.dFFSR.reset_set_flag (start = 1) slice: {} (2|2) Unmatched Equations *************************** [ALGO] (1) ($RES_SIM_3) [----] if initial() then [----] assert(true, "Invalid size of table (n < 1)", AssertionLevel.error); [----] for i in 1:1 loop [----] end for; [----] end if; [----] data_1.y := data_1.y0; [----] for i in 1:1 loop [----] if time >= data_1.t[i] then [----] data_1.y := data_1.x[i]; [----] end if; [----] end for; slice: {} [ALGO] (8) ($RES_SIM_0) [----] if (change(dFFREGSRL.dFFSR.clock) or change(dFFREGSRL.dFFSR.reset)) or change(dFFREGSRL.dFFSR.set) then [----] if change(dFFREGSRL.dFFSR.clock) then [----] if initial() then [----] dFFREGSRL.dFFSR.clock_flag := ({0, 0, 0, 2, 0, 0, 0, 2, 0})[dFFREGSRL.dFFSR.clock]; [----] elseif true then [----] dFFREGSRL.dFFSR.clock_flag := ({{0, 0, 0, 2, 0, 0, 0, 2, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}, {2, 2, 0, 1, 2, 2, 0, 1, 2}, {0, 0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}, {2, 2, 0, 1, 2, 2, 0, 1, 0}, {0, 0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}})[$PRE.dFFREGSRL.dFFSR.clock, dFFREGSRL.dFFSR.clock]; [----] end if; [----] end if; [----] dFFREGSRL.dFFSR.reset_set_flag := dFFREGSRL.dFFSR.ResetSetMap[dFFREGSRL.dFFSR.reset, dFFREGSRL.dFFSR.set]; [----] for i in 1:2 loop [----] if dFFREGSRL.dFFSR.reset_set_flag == 1 then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U'; [----] elseif dFFREGSRL.dFFSR.reset_set_flag == 2 then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'1'; [----] elseif dFFREGSRL.dFFSR.reset_set_flag == 3 then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'0'; [----] elseif dFFREGSRL.dFFSR.reset_set_flag == 4 then [----] if dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 1 or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 0 then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U'; [----] elseif true then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X'; [----] end if; [----] elseif dFFREGSRL.dFFSR.reset_set_flag == 5 then [----] if dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'1' and ((dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'1' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'H') or dFFREGSRL.dFFSR.clock_flag == 0) then [----] #UNKNOWN STATEMENT#; [----] elseif (dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'1' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'H') and dFFREGSRL.dFFSR.clock_flag == 1 then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'1'; [----] elseif dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 1 or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 0 then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U'; [----] elseif true then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X'; [----] end if; [----] elseif dFFREGSRL.dFFSR.reset_set_flag == 6 then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X'; [----] elseif dFFREGSRL.dFFSR.reset_set_flag == 7 then [----] if dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' and ((dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'L') or dFFREGSRL.dFFSR.clock_flag == 0) then [----] #UNKNOWN STATEMENT#; [----] elseif (dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'L') and dFFREGSRL.dFFSR.clock_flag == 1 then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'0'; [----] elseif dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 1 or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 0 then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U'; [----] elseif true then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X'; [----] end if; [----] elseif dFFREGSRL.dFFSR.reset_set_flag == 8 then [----] if dFFREGSRL.dFFSR.clock_flag == 0 then [----] #UNKNOWN STATEMENT#; [----] elseif dFFREGSRL.dFFSR.clock_flag == 1 then [----] dFFREGSRL.dFFSR.nextstate[i] := ({{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}})[dFFREGSRL.dFFSR.dataIn[i], Modelica.Electrical.Digital.Interfaces.Strength.'S_X01']; [----] elseif true then [----] if dFFREGSRL.dFFSR.next_assign_val[i] == ({{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}})[dFFREGSRL.dFFSR.dataIn[i], Modelica.Electrical.Digital.Interfaces.Strength.'S_X01'] or dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' then [----] #UNKNOWN STATEMENT#; [----] elseif dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U'; [----] elseif true then [----] dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X'; [----] end if; [----] end if; [----] end if; [----] end for; [----] end if; [----] dFFREGSRL.dFFSR.next_assign_val := dFFREGSRL.dFFSR.nextstate; [----] dFFREGSRL.dFFSR.dataOut := dFFREGSRL.dFFSR.nextstate; slice: {7}