Running: ./testmodel.py --libraries=/home/hudson/saved_omc/libraries/.openmodelica/libraries --ompython_omhome=/usr Modelica_3.2.2_Modelica.Electrical.Digital.Examples.DLATREGL.conf.json loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo", uses=false) loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo", uses=false) loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo", uses=false) Using package Modelica with version 3.2.3 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo) Using package Complex with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo) Using package ModelicaServices with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo) Running command: translateModel(Modelica.Electrical.Digital.Examples.DLATREGL,tolerance=1e-06,outputFormat="empty",numberOfIntervals=5000,variableFilter="",fileNamePrefix="Modelica_3.2.2_Modelica.Electrical.Digital.Examples.DLATREGL") translateModel(Modelica.Electrical.Digital.Examples.DLATREGL,tolerance=1e-06,outputFormat="empty",numberOfIntervals=5000,variableFilter="",fileNamePrefix="Modelica_3.2.2_Modelica.Electrical.Digital.Examples.DLATREGL") Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo): time 0.001152/0.001152, allocations: 115.3 kB / 17.75 MB, free: 5.195 MB / 14.72 MB Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo): time 0.001152/0.001152, allocations: 189.9 kB / 18.68 MB, free: 4.27 MB / 14.72 MB Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo): time 1.314/1.314, allocations: 205.1 MB / 224.6 MB, free: 12.24 MB / 190.1 MB Notification: Performance of FrontEnd - Absyn->SCode: time 1.871e-05/1.871e-05, allocations: 3.266 kB / 328.5 MB, free: 3.355 MB / 270.1 MB Notification: Performance of NFInst.instantiate(Modelica.Electrical.Digital.Examples.DLATREGL): time 0.002254/0.002281, allocations: 1.745 MB / 330.2 MB, free: 1.602 MB / 270.1 MB Notification: Performance of NFInst.instExpressions: time 0.001876/0.00417, allocations: 1.011 MB / 331.3 MB, free: 0.582 MB / 270.1 MB Notification: Performance of NFInst.updateImplicitVariability: time 6.435e-05/0.004246, allocations: 3.938 kB / 331.3 MB, free: 0.5781 MB / 270.1 MB Notification: Performance of NFTyping.typeComponents: time 0.0001377/0.004391, allocations: 27.78 kB / 331.3 MB, free: 0.5508 MB / 270.1 MB Notification: Performance of NFTyping.typeBindings: time 0.000121/0.004526, allocations: 35.72 kB / 331.3 MB, free: 0.5156 MB / 270.1 MB Notification: Performance of NFTyping.typeClassSections: time 0.0002541/0.004788, allocations: 115.8 kB / 331.4 MB, free: 412 kB / 270.1 MB Notification: Performance of NFFlatten.flatten: time 0.0005149/0.005312, allocations: 495.4 kB / 331.9 MB, free: 15.91 MB / 286.1 MB Notification: Performance of NFFlatten.resolveConnections: time 0.0001494/0.005471, allocations: 81.58 kB / 332 MB, free: 15.83 MB / 286.1 MB Notification: Performance of NFEvalConstants.evaluate: time 0.0006132/0.006091, allocations: 0.7134 MB / 332.7 MB, free: 15.12 MB / 286.1 MB Notification: Performance of NFSimplifyModel.simplify: time 0.0001741/0.006275, allocations: 127.6 kB / 332.8 MB, free: 15 MB / 286.1 MB Notification: Performance of NFPackage.collectConstants: time 5.992e-05/0.006342, allocations: 28 kB / 332.9 MB, free: 14.97 MB / 286.1 MB Notification: Performance of NFFlatten.collectFunctions: time 5.496e-05/0.006402, allocations: 32 kB / 332.9 MB, free: 14.94 MB / 286.1 MB Notification: Performance of combineBinaries: time 0.0002664/0.006673, allocations: 340.8 kB / 333.2 MB, free: 14.6 MB / 286.1 MB Notification: Performance of replaceArrayConstructors: time 8.94e-05/0.006769, allocations: 185.4 kB / 333.4 MB, free: 14.42 MB / 286.1 MB Notification: Performance of NFVerifyModel.verify: time 7.665e-05/0.006851, allocations: 43.94 kB / 333.4 MB, free: 14.38 MB / 286.1 MB Notification: Performance of FrontEnd: time 1.877e-05/0.006875, allocations: 7.938 kB / 333.5 MB, free: 14.37 MB / 286.1 MB Notification: Model statistics after passing the front-end and creating the data structures used by the back-end: * Number of equations: 40 (19) * Number of variables: 40 (25) Notification: Performance of Bindings: time 0.001029/0.007909, allocations: 1.135 MB / 334.6 MB, free: 13.13 MB / 286.1 MB Notification: Performance of FunctionAlias: time 0.000154/0.008069, allocations: 111.8 kB / 334.7 MB, free: 13.02 MB / 286.1 MB Notification: Performance of Early Inline: time 0.0008242/0.008902, allocations: 0.8865 MB / 335.6 MB, free: 12.11 MB / 286.1 MB Notification: Performance of simplify1: time 1.446e-05/0.008923, allocations: 11.98 kB / 335.6 MB, free: 12.09 MB / 286.1 MB Notification: Performance of Alias: time 0.0006946/0.009623, allocations: 0.619 MB / 336.2 MB, free: 11.42 MB / 286.1 MB Notification: Performance of simplify2: time 7.274e-06/0.00964, allocations: 4 kB / 336.2 MB, free: 11.41 MB / 286.1 MB Notification: Performance of Events: time 0.0007653/0.01041, allocations: 0.8383 MB / 337.1 MB, free: 10.38 MB / 286.1 MB Notification: Performance of Detect States: time 0.0005618/0.01098, allocations: 379.9 kB / 337.4 MB, free: 9.996 MB / 286.1 MB Notification: Performance of Partitioning: time 0.0002825/0.01127, allocations: 256 kB / 337.7 MB, free: 9.738 MB / 286.1 MB Error: Internal error NBResolveSingularities.noIndexReduction failed. (2|2) Unmatched Variables *************************** [DISC] (1) protected Integer dLATREGL.dLATR.reset_flag (start = 1) slice: {} [DISC] (1) protected Integer dLATREGL.dLATR.enable_flag (start = 0) slice: {} (1|2) Unmatched Equations *************************** [ALGO] (8) ($RES_SIM_0) [----] if enable.y == Modelica.Electrical.Digital.Interfaces.Logic.'1' or enable.y == Modelica.Electrical.Digital.Interfaces.Logic.'H' then [----] dLATREGL.dLATR.enable_flag := 1; [----] elseif enable.y == Modelica.Electrical.Digital.Interfaces.Logic.'0' or enable.y == Modelica.Electrical.Digital.Interfaces.Logic.'L' then [----] dLATREGL.dLATR.enable_flag := 0; [----] elseif enable.y == Modelica.Electrical.Digital.Interfaces.Logic.'U' then [----] dLATREGL.dLATR.enable_flag := 3; [----] elseif true then [----] dLATREGL.dLATR.enable_flag := 2; [----] end if; [----] dLATREGL.dLATR.reset_flag := dLATREGL.dLATR.ResetMap[reset.y]; [----] for i in 1:2 loop [----] if dLATREGL.dLATR.reset_flag == 1 then [----] dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U'; [----] elseif dLATREGL.dLATR.reset_flag == 2 then [----] dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'0'; [----] elseif dLATREGL.dLATR.reset_flag == 3 then [----] if dLATREGL.dLATR.enable_flag == 0 then [----] #UNKNOWN STATEMENT#; [----] elseif dLATREGL.dLATR.enable_flag == 3 then [----] dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U'; [----] elseif dLATREGL.dLATR.enable_flag == 1 then [----] dLATREGL.dLATR.nextstate[i] := ({{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}})[dLATREGL.dLATR.dataIn[i], Modelica.Electrical.Digital.Interfaces.Strength.'S_X01']; [----] elseif true then [----] if dLATREGL.dLATR.next_assign_val[i] == ({{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}})[dLATREGL.dLATR.dataIn[i], Modelica.Electrical.Digital.Interfaces.Strength.'S_X01'] or dLATREGL.dLATR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' then [----] #UNKNOWN STATEMENT#; [----] elseif dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' then [----] dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U'; [----] elseif true then [----] dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X'; [----] end if; [----] end if; [----] elseif dLATREGL.dLATR.reset_flag == 4 then [----] if (dLATREGL.dLATR.enable_flag == 3 or dLATREGL.dLATR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dLATREGL.dLATR.enable_flag <> 1) or dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dLATREGL.dLATR.enable_flag <> 0 then [----] dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U'; [----] elseif dLATREGL.dLATR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' and ((dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'L') or dLATREGL.dLATR.enable_flag == 0) then [----] #UNKNOWN STATEMENT#; [----] elseif (dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'L') and dLATREGL.dLATR.enable_flag == 1 then [----] dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'0'; [----] elseif true then [----] dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X'; [----] end if; [----] end if; [----] end for; [----] dLATREGL.dLATR.next_assign_val := dLATREGL.dLATR.nextstate; [----] dLATREGL.dLATR.dataOut := dLATREGL.dLATR.nextstate; slice: {6, 7}