Running: ./testmodel.py --libraries=/home/hudson/saved_omc/libraries/.openmodelica/libraries --ompython_omhome=/usr Modelica_3.2.1_Modelica.Electrical.Digital.Examples.DFFREGSRL.conf.json
loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo", uses=false)
loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo", uses=false)
loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo", uses=false)
Using package Modelica with version 3.2.3 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo)
Using package Complex with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo)
Using package ModelicaServices with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo)
Running command: translateModel(Modelica.Electrical.Digital.Examples.DFFREGSRL,tolerance=1e-06,outputFormat="empty",numberOfIntervals=5000,variableFilter="",fileNamePrefix="Modelica_3.2.1_Modelica.Electrical.Digital.Examples.DFFREGSRL")
translateModel(Modelica.Electrical.Digital.Examples.DFFREGSRL,tolerance=1e-06,outputFormat="empty",numberOfIntervals=5000,variableFilter="",fileNamePrefix="Modelica_3.2.1_Modelica.Electrical.Digital.Examples.DFFREGSRL")
Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo): time 0.001251/0.001251, allocations: 107.1 kB / 16.42 MB, free: 6.031 MB / 14.72 MB
Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo): time 0.001136/0.001136, allocations: 186.6 kB / 17.35 MB, free: 5.602 MB / 14.72 MB
Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo): time 1.252/1.252, allocations: 205.1 MB / 223.2 MB, free: 12.23 MB / 190.1 MB
Notification: Performance of FrontEnd - Absyn->SCode: time 1.575e-05/1.576e-05, allocations: 3.266 kB / 327.2 MB, free: 3.336 MB / 270.1 MB
Notification: Performance of NFInst.instantiate(Modelica.Electrical.Digital.Examples.DFFREGSRL): time 0.002197/0.002221, allocations: 1.813 MB / 329 MB, free: 1.512 MB / 270.1 MB
Notification: Performance of NFInst.instExpressions: time 0.00192/0.004151, allocations: 1.07 MB / 330.1 MB, free: 444 kB / 270.1 MB
Notification: Performance of NFInst.updateImplicitVariability: time 6.219e-05/0.004225, allocations: 7.938 kB / 330.1 MB, free: 436 kB / 270.1 MB
Notification: Performance of NFTyping.typeComponents: time 0.0001198/0.00435, allocations: 35.77 kB / 330.1 MB, free: 400 kB / 270.1 MB
Notification: Performance of NFTyping.typeBindings: time 0.0002101/0.004572, allocations: 167.4 kB / 330.3 MB, free: 232 kB / 270.1 MB
Notification: Performance of NFTyping.typeClassSections: time 0.0002526/0.004833, allocations: 143.8 kB / 330.4 MB, free: 88 kB / 270.1 MB
Notification: Performance of NFFlatten.flatten: time 0.0006025/0.005443, allocations: 0.6592 MB / 331.1 MB, free: 15.43 MB / 286.1 MB
Notification: Performance of NFFlatten.resolveConnections: time 0.0001528/0.005605, allocations: 94.14 kB / 331.2 MB, free: 15.33 MB / 286.1 MB
Notification: Performance of NFEvalConstants.evaluate: time 0.0009286/0.00654, allocations: 1.217 MB / 332.4 MB, free: 14.11 MB / 286.1 MB
Notification: Performance of NFSimplifyModel.simplify: time 0.0002086/0.006758, allocations: 187.3 kB / 332.6 MB, free: 13.93 MB / 286.1 MB
Notification: Performance of NFPackage.collectConstants: time 7.236e-05/0.006839, allocations: 43.98 kB / 332.6 MB, free: 13.89 MB / 286.1 MB
Notification: Performance of NFFlatten.collectFunctions: time 6.632e-05/0.00691, allocations: 36 kB / 332.6 MB, free: 13.85 MB / 286.1 MB
Notification: Performance of combineBinaries: time 0.0003434/0.007259, allocations: 420.2 kB / 333 MB, free: 13.44 MB / 286.1 MB
Notification: Performance of replaceArrayConstructors: time 0.0001113/0.007376, allocations: 193.1 kB / 333.2 MB, free: 13.25 MB / 286.1 MB
Notification: Performance of NFVerifyModel.verify: time 8.266e-05/0.007463, allocations: 59.88 kB / 333.3 MB, free: 13.19 MB / 286.1 MB
Notification: Performance of FrontEnd: time 1.77e-05/0.007486, allocations: 7.938 kB / 333.3 MB, free: 13.18 MB / 286.1 MB
Notification: Model statistics after passing the front-end and creating the data structures used by the back-end:
 * Number of equations: 43 (22)
 * Number of variables: 43 (28)
Notification: Performance of Bindings: time 0.001189/0.008679, allocations: 1.337 MB / 334.6 MB, free: 11.74 MB / 286.1 MB
Notification: Performance of FunctionAlias: time 0.0001638/0.008849, allocations: 143.7 kB / 334.8 MB, free: 11.6 MB / 286.1 MB
Notification: Performance of Early Inline: time 0.001016/0.009873, allocations: 1.109 MB / 335.9 MB, free: 10.46 MB / 286.1 MB
Notification: Performance of simplify1: time 1.122e-05/0.009893, allocations: 11.98 kB / 335.9 MB, free: 10.45 MB / 286.1 MB
Notification: Performance of Alias: time 0.0007916/0.01069, allocations: 0.7599 MB / 336.7 MB, free: 9.629 MB / 286.1 MB
Notification: Performance of simplify2: time 7.124e-06/0.0107, allocations: 4 kB / 336.7 MB, free: 9.625 MB / 286.1 MB
Notification: Performance of Events: time 0.0007634/0.01147, allocations: 0.7475 MB / 337.4 MB, free: 8.77 MB / 286.1 MB
Notification: Performance of Detect States: time 0.0004747/0.01196, allocations: 487.7 kB / 337.9 MB, free: 8.277 MB / 286.1 MB
Notification: Performance of Partitioning: time 0.0002869/0.01225, allocations: 279.9 kB / 338.2 MB, free: 7.996 MB / 286.1 MB
Error: Internal error NBResolveSingularities.noIndexReduction failed.
(2|2) Unmatched Variables
***************************
        [DISC] (1) protected Integer dFFREGSRL.dFFSR.clock_flag (start = 0)
         slice: {}
        [DISC] (1) protected Integer dFFREGSRL.dFFSR.reset_set_flag (start = 1)
         slice: {}

(2|2) Unmatched Equations
***************************
        [ALGO] (1) ($RES_SIM_3)
[----] if initial() then
[----]   assert(true, "Invalid size of table (n < 1)", AssertionLevel.error);

[----]   for i in 1:1 loop
[----]   end for;
[----] end if;

[----] data_1.y := data_1.y0;

[----] for i in 1:1 loop
[----]   if time >= data_1.t[i] then
[----]     data_1.y := data_1.x[i];
[----]   end if;
[----] end for;

         slice: {}
        [ALGO] (8) ($RES_SIM_0)
[----] if (change(dFFREGSRL.dFFSR.clock) or change(dFFREGSRL.dFFSR.reset)) or change(dFFREGSRL.dFFSR.set) then
[----]   if change(dFFREGSRL.dFFSR.clock) then
[----]     if initial() then
[----]       dFFREGSRL.dFFSR.clock_flag := ({0, 0, 0, 2, 0, 0, 0, 2, 0})[dFFREGSRL.dFFSR.clock];
[----]     elseif true then
[----]       dFFREGSRL.dFFSR.clock_flag := ({{0, 0, 0, 2, 0, 0, 0, 2, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}, {2, 2, 0, 1, 2, 2, 0, 1, 2}, {0, 0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}, {2, 2, 0, 1, 2, 2, 0, 1, 0}, {0, 0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}})[$PRE.dFFREGSRL.dFFSR.clock, dFFREGSRL.dFFSR.clock];
[----]     end if;
[----]   end if;

[----]   dFFREGSRL.dFFSR.reset_set_flag := dFFREGSRL.dFFSR.ResetSetMap[dFFREGSRL.dFFSR.reset, dFFREGSRL.dFFSR.set];

[----]   for i in 1:2 loop
[----]     if dFFREGSRL.dFFSR.reset_set_flag == 1 then
[----]       dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 2 then
[----]       dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'1';
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 3 then
[----]       dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'0';
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 4 then
[----]       if dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 1 or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 0 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]       elseif true then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]       end if;
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 5 then
[----]       if dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'1' and ((dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'1' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'H') or dFFREGSRL.dFFSR.clock_flag == 0) then
[----]         #UNKNOWN STATEMENT#;
[----]       elseif (dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'1' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'H') and dFFREGSRL.dFFSR.clock_flag == 1 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'1';
[----]       elseif dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 1 or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 0 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]       elseif true then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]       end if;
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 6 then
[----]       dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 7 then
[----]       if dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' and ((dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'L') or dFFREGSRL.dFFSR.clock_flag == 0) then
[----]         #UNKNOWN STATEMENT#;
[----]       elseif (dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'L') and dFFREGSRL.dFFSR.clock_flag == 1 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'0';
[----]       elseif dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 1 or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 0 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]       elseif true then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]       end if;
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 8 then
[----]       if dFFREGSRL.dFFSR.clock_flag == 0 then
[----]         #UNKNOWN STATEMENT#;
[----]       elseif dFFREGSRL.dFFSR.clock_flag == 1 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := ({{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}})[dFFREGSRL.dFFSR.dataIn[i], Modelica.Electrical.Digital.Interfaces.Strength.'S_X01'];
[----]       elseif true then
[----]         if dFFREGSRL.dFFSR.next_assign_val[i] == ({{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}})[dFFREGSRL.dFFSR.dataIn[i], Modelica.Electrical.Digital.Interfaces.Strength.'S_X01'] or dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' then
[----]           #UNKNOWN STATEMENT#;
[----]         elseif dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' then
[----]           dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]         elseif true then
[----]           dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]         end if;
[----]       end if;
[----]     end if;
[----]   end for;
[----] end if;

[----] dFFREGSRL.dFFSR.next_assign_val := dFFREGSRL.dFFSR.nextstate;
[----] dFFREGSRL.dFFSR.dataOut := dFFREGSRL.dFFSR.nextstate;

         slice: {7}