Running: ./testmodel.py --libraries=/home/hudson/saved_omc/libraries/.openmodelica/libraries --ompython_omhome=/usr Modelica_3.1_Modelica.Electrical.Digital.Examples.DLATREGL.conf.json
loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo", uses=false)
loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo", uses=false)
loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo", uses=false)
Using package Modelica with version 3.2.3 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo)
Using package Complex with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo)
Using package ModelicaServices with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo)
Running command: translateModel(Modelica.Electrical.Digital.Examples.DLATREGL,tolerance=1e-06,outputFormat="empty",numberOfIntervals=5000,variableFilter="",fileNamePrefix="Modelica_3.1_Modelica.Electrical.Digital.Examples.DLATREGL")
translateModel(Modelica.Electrical.Digital.Examples.DLATREGL,tolerance=1e-06,outputFormat="empty",numberOfIntervals=5000,variableFilter="",fileNamePrefix="Modelica_3.1_Modelica.Electrical.Digital.Examples.DLATREGL")
Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo): time 0.001252/0.001259, allocations: 102.4 kB / 16.42 MB, free: 6.504 MB / 14.72 MB
Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo): time 0.001316/0.001316, allocations: 192.2 kB / 17.35 MB, free: 5.754 MB / 14.72 MB
Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo): time 1.351/1.351, allocations: 205.1 MB / 223.2 MB, free: 12.24 MB / 190.1 MB
Notification: Performance of FrontEnd - Absyn->SCode: time 2.128e-05/2.129e-05, allocations: 6.219 kB / 327.2 MB, free: 3.352 MB / 270.1 MB
Notification: Performance of NFInst.instantiate(Modelica.Electrical.Digital.Examples.DLATREGL): time 0.002347/0.002376, allocations: 1.747 MB / 328.9 MB, free: 1.594 MB / 270.1 MB
Notification: Performance of NFInst.instExpressions: time 0.00199/0.004377, allocations: 1.003 MB / 329.9 MB, free: 0.582 MB / 270.1 MB
Notification: Performance of NFInst.updateImplicitVariability: time 0.0001129/0.004502, allocations: 7.938 kB / 329.9 MB, free: 0.5742 MB / 270.1 MB
Notification: Performance of NFTyping.typeComponents: time 0.0001441/0.004652, allocations: 27.78 kB / 330 MB, free: 0.5469 MB / 270.1 MB
Notification: Performance of NFTyping.typeBindings: time 0.0001309/0.004798, allocations: 31.72 kB / 330 MB, free: 0.5156 MB / 270.1 MB
Notification: Performance of NFTyping.typeClassSections: time 0.0002981/0.005104, allocations: 115.8 kB / 330.1 MB, free: 412 kB / 270.1 MB
Notification: Performance of NFFlatten.flatten: time 0.0005909/0.005703, allocations: 491.4 kB / 330.6 MB, free: 15.92 MB / 286.1 MB
Notification: Performance of NFFlatten.resolveConnections: time 0.0001604/0.005873, allocations: 73.64 kB / 330.7 MB, free: 15.84 MB / 286.1 MB
Notification: Performance of NFEvalConstants.evaluate: time 0.0006976/0.006578, allocations: 0.7212 MB / 331.4 MB, free: 15.12 MB / 286.1 MB
Notification: Performance of NFSimplifyModel.simplify: time 0.0002306/0.006819, allocations: 127.6 kB / 331.5 MB, free: 15 MB / 286.1 MB
Notification: Performance of NFPackage.collectConstants: time 7.359e-05/0.0069, allocations: 28 kB / 331.5 MB, free: 14.97 MB / 286.1 MB
Notification: Performance of NFFlatten.collectFunctions: time 6.269e-05/0.006968, allocations: 28 kB / 331.6 MB, free: 14.95 MB / 286.1 MB
Notification: Performance of combineBinaries: time 0.0002855/0.00726, allocations: 344.8 kB / 331.9 MB, free: 14.61 MB / 286.1 MB
Notification: Performance of replaceArrayConstructors: time 0.000112/0.007378, allocations: 181.4 kB / 332.1 MB, free: 14.43 MB / 286.1 MB
Notification: Performance of NFVerifyModel.verify: time 8.011e-05/0.007464, allocations: 43.94 kB / 332.1 MB, free: 14.38 MB / 286.1 MB
Notification: Performance of FrontEnd: time 2.85e-05/0.007497, allocations: 7.938 kB / 332.1 MB, free: 14.38 MB / 286.1 MB
Notification: Model statistics after passing the front-end and creating the data structures used by the back-end:
 * Number of equations: 40 (19)
 * Number of variables: 40 (25)
Notification: Performance of Bindings: time 0.001189/0.008691, allocations: 1.147 MB / 333.3 MB, free: 13.12 MB / 286.1 MB
Notification: Performance of FunctionAlias: time 0.0001851/0.008883, allocations: 111.8 kB / 333.4 MB, free: 13.02 MB / 286.1 MB
Notification: Performance of Early Inline: time 0.0009293/0.00982, allocations: 0.8864 MB / 334.3 MB, free: 12.1 MB / 286.1 MB
Notification: Performance of simplify1: time 1.798e-05/0.009845, allocations: 7.984 kB / 334.3 MB, free: 12.09 MB / 286.1 MB
Notification: Performance of Alias: time 0.0007966/0.01065, allocations: 0.6151 MB / 334.9 MB, free: 11.42 MB / 286.1 MB
Notification: Performance of simplify2: time 7.895e-06/0.01066, allocations: 0 / 334.9 MB, free: 11.42 MB / 286.1 MB
Notification: Performance of Events: time 0.000872/0.01154, allocations: 0.8566 MB / 335.7 MB, free: 10.38 MB / 286.1 MB
Notification: Performance of Detect States: time 0.0004475/0.012, allocations: 375.9 kB / 336.1 MB, free: 9.992 MB / 286.1 MB
Notification: Performance of Partitioning: time 0.0003173/0.01233, allocations: 252 kB / 336.4 MB, free: 9.738 MB / 286.1 MB
Error: Internal error NBResolveSingularities.noIndexReduction failed.
(2|2) Unmatched Variables
***************************
        [DISC] (1) protected Integer dLATREGL.dLATR.reset_flag (start = 1)
         slice: {}
        [DISC] (1) protected Integer dLATREGL.dLATR.enable_flag (start = 0)
         slice: {}

(1|2) Unmatched Equations
***************************
        [ALGO] (8) ($RES_SIM_0)
[----] if enable.y == Modelica.Electrical.Digital.Interfaces.Logic.'1' or enable.y == Modelica.Electrical.Digital.Interfaces.Logic.'H' then
[----]   dLATREGL.dLATR.enable_flag := 1;
[----] elseif enable.y == Modelica.Electrical.Digital.Interfaces.Logic.'0' or enable.y == Modelica.Electrical.Digital.Interfaces.Logic.'L' then
[----]   dLATREGL.dLATR.enable_flag := 0;
[----] elseif enable.y == Modelica.Electrical.Digital.Interfaces.Logic.'U' then
[----]   dLATREGL.dLATR.enable_flag := 3;
[----] elseif true then
[----]   dLATREGL.dLATR.enable_flag := 2;
[----] end if;

[----] dLATREGL.dLATR.reset_flag := dLATREGL.dLATR.ResetMap[reset.y];

[----] for i in 1:2 loop
[----]   if dLATREGL.dLATR.reset_flag == 1 then
[----]     dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]   elseif dLATREGL.dLATR.reset_flag == 2 then
[----]     dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'0';
[----]   elseif dLATREGL.dLATR.reset_flag == 3 then
[----]     if dLATREGL.dLATR.enable_flag == 0 then
[----]       #UNKNOWN STATEMENT#;
[----]     elseif dLATREGL.dLATR.enable_flag == 3 then
[----]       dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]     elseif dLATREGL.dLATR.enable_flag == 1 then
[----]       dLATREGL.dLATR.nextstate[i] := ({{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}})[dLATREGL.dLATR.dataIn[i], Modelica.Electrical.Digital.Interfaces.Strength.'S_X01'];
[----]     elseif true then
[----]       if dLATREGL.dLATR.next_assign_val[i] == ({{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}})[dLATREGL.dLATR.dataIn[i], Modelica.Electrical.Digital.Interfaces.Strength.'S_X01'] or dLATREGL.dLATR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' then
[----]         #UNKNOWN STATEMENT#;
[----]       elseif dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' then
[----]         dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]       elseif true then
[----]         dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]       end if;
[----]     end if;
[----]   elseif dLATREGL.dLATR.reset_flag == 4 then
[----]     if (dLATREGL.dLATR.enable_flag == 3 or dLATREGL.dLATR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dLATREGL.dLATR.enable_flag <> 1) or dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dLATREGL.dLATR.enable_flag <> 0 then
[----]       dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]     elseif dLATREGL.dLATR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' and ((dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'L') or dLATREGL.dLATR.enable_flag == 0) then
[----]       #UNKNOWN STATEMENT#;
[----]     elseif (dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dLATREGL.dLATR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'L') and dLATREGL.dLATR.enable_flag == 1 then
[----]       dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'0';
[----]     elseif true then
[----]       dLATREGL.dLATR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]     end if;
[----]   end if;
[----] end for;

[----] dLATREGL.dLATR.next_assign_val := dLATREGL.dLATR.nextstate;
[----] dLATREGL.dLATR.dataOut := dLATREGL.dLATR.nextstate;

         slice: {6, 7}