Running: ./testmodel.py --libraries=/home/hudson/saved_omc/libraries/.openmodelica/libraries --ompython_omhome=/usr Modelica_3.1_Modelica.Electrical.Digital.Examples.DFFREGSRL.conf.json
loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo", uses=false)
loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo", uses=false)
loadFile("/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo", uses=false)
Using package Modelica with version 3.2.3 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo)
Using package Complex with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo)
Using package ModelicaServices with version 4.0.0 (/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo)
Running command: translateModel(Modelica.Electrical.Digital.Examples.DFFREGSRL,tolerance=1e-06,outputFormat="empty",numberOfIntervals=5000,variableFilter="",fileNamePrefix="Modelica_3.1_Modelica.Electrical.Digital.Examples.DFFREGSRL")
translateModel(Modelica.Electrical.Digital.Examples.DFFREGSRL,tolerance=1e-06,outputFormat="empty",numberOfIntervals=5000,variableFilter="",fileNamePrefix="Modelica_3.1_Modelica.Electrical.Digital.Examples.DFFREGSRL")
Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/ModelicaServices 4.0.0+maint.om/package.mo): time 0.001199/0.001199, allocations: 106.8 kB / 16.42 MB, free: 6.035 MB / 14.72 MB
Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/Complex 4.0.0+maint.om/package.mo): time 0.001093/0.001093, allocations: 190.6 kB / 17.35 MB, free: 5.598 MB / 14.72 MB
Notification: Performance of loadFile(/home/hudson/saved_omc/libraries/.openmodelica/libraries/Modelica 3.2.3+maint.om/package.mo): time 1.313/1.313, allocations: 205.1 MB / 223.2 MB, free: 12.27 MB / 190.1 MB
Notification: Performance of FrontEnd - Absyn->SCode: time 2.354e-05/2.355e-05, allocations: 3.125 kB / 327.2 MB, free: 3.332 MB / 270.1 MB
Notification: Performance of NFInst.instantiate(Modelica.Electrical.Digital.Examples.DFFREGSRL): time 0.002486/0.002517, allocations: 1.809 MB / 329 MB, free: 1.512 MB / 270.1 MB
Notification: Performance of NFInst.instExpressions: time 0.002086/0.004614, allocations: 1.07 MB / 330.1 MB, free: 444 kB / 270.1 MB
Notification: Performance of NFInst.updateImplicitVariability: time 7.473e-05/0.004701, allocations: 4 kB / 330.1 MB, free: 440 kB / 270.1 MB
Notification: Performance of NFTyping.typeComponents: time 0.0001565/0.004864, allocations: 31.72 kB / 330.1 MB, free: 408 kB / 270.1 MB
Notification: Performance of NFTyping.typeBindings: time 0.0002448/0.005124, allocations: 175.4 kB / 330.3 MB, free: 232 kB / 270.1 MB
Notification: Performance of NFTyping.typeClassSections: time 0.0003068/0.005439, allocations: 139.8 kB / 330.4 MB, free: 92 kB / 270.1 MB
Notification: Performance of NFFlatten.flatten: time 0.0006472/0.006095, allocations: 0.6631 MB / 331.1 MB, free: 15.43 MB / 286.1 MB
Notification: Performance of NFFlatten.resolveConnections: time 0.0001888/0.006293, allocations: 98.19 kB / 331.2 MB, free: 15.33 MB / 286.1 MB
Notification: Performance of NFEvalConstants.evaluate: time 0.0009907/0.00729, allocations: 1.217 MB / 332.4 MB, free: 14.11 MB / 286.1 MB
Notification: Performance of NFSimplifyModel.simplify: time 0.0002277/0.007528, allocations: 183.3 kB / 332.6 MB, free: 13.93 MB / 286.1 MB
Notification: Performance of NFPackage.collectConstants: time 7.872e-05/0.007616, allocations: 40 kB / 332.6 MB, free: 13.89 MB / 286.1 MB
Notification: Performance of NFFlatten.collectFunctions: time 6.949e-05/0.007691, allocations: 36 kB / 332.6 MB, free: 13.86 MB / 286.1 MB
Notification: Performance of combineBinaries: time 0.000375/0.008072, allocations: 420.2 kB / 333 MB, free: 13.44 MB / 286.1 MB
Notification: Performance of replaceArrayConstructors: time 0.0001191/0.008197, allocations: 197.2 kB / 333.2 MB, free: 13.25 MB / 286.1 MB
Notification: Performance of NFVerifyModel.verify: time 9.003e-05/0.008292, allocations: 55.88 kB / 333.3 MB, free: 13.19 MB / 286.1 MB
Notification: Performance of FrontEnd: time 2.883e-05/0.008327, allocations: 11.88 kB / 333.3 MB, free: 13.18 MB / 286.1 MB
Notification: Model statistics after passing the front-end and creating the data structures used by the back-end:
 * Number of equations: 43 (22)
 * Number of variables: 43 (28)
Notification: Performance of Bindings: time 0.001302/0.009633, allocations: 1.333 MB / 334.6 MB, free: 11.74 MB / 286.1 MB
Notification: Performance of FunctionAlias: time 0.0001884/0.009828, allocations: 143.7 kB / 334.8 MB, free: 11.6 MB / 286.1 MB
Notification: Performance of Early Inline: time 0.001079/0.01091, allocations: 1.105 MB / 335.9 MB, free: 10.47 MB / 286.1 MB
Notification: Performance of simplify1: time 1.452e-05/0.01094, allocations: 16 kB / 335.9 MB, free: 10.45 MB / 286.1 MB
Notification: Performance of Alias: time 0.000926/0.01187, allocations: 0.7599 MB / 336.7 MB, free: 9.633 MB / 286.1 MB
Notification: Performance of simplify2: time 7.564e-06/0.01189, allocations: 4 kB / 336.7 MB, free: 9.629 MB / 286.1 MB
Notification: Performance of Events: time 0.0008368/0.01273, allocations: 0.7514 MB / 337.4 MB, free: 8.77 MB / 286.1 MB
Notification: Performance of Detect States: time 0.0007276/0.01347, allocations: 479.7 kB / 337.9 MB, free: 8.285 MB / 286.1 MB
Notification: Performance of Partitioning: time 0.0003337/0.01381, allocations: 291.9 kB / 338.2 MB, free: 7.992 MB / 286.1 MB
Error: Internal error NBResolveSingularities.noIndexReduction failed.
(2|2) Unmatched Variables
***************************
        [DISC] (1) protected Integer dFFREGSRL.dFFSR.clock_flag (start = 0)
         slice: {}
        [DISC] (1) protected Integer dFFREGSRL.dFFSR.reset_set_flag (start = 1)
         slice: {}

(2|2) Unmatched Equations
***************************
        [ALGO] (1) ($RES_SIM_3)
[----] if initial() then
[----]   assert(true, "Invalid size of table (n < 1)", AssertionLevel.error);

[----]   for i in 1:1 loop
[----]   end for;
[----] end if;

[----] data_1.y := data_1.y0;

[----] for i in 1:1 loop
[----]   if time >= data_1.t[i] then
[----]     data_1.y := data_1.x[i];
[----]   end if;
[----] end for;

         slice: {}
        [ALGO] (8) ($RES_SIM_0)
[----] if (change(dFFREGSRL.dFFSR.clock) or change(dFFREGSRL.dFFSR.reset)) or change(dFFREGSRL.dFFSR.set) then
[----]   if change(dFFREGSRL.dFFSR.clock) then
[----]     if initial() then
[----]       dFFREGSRL.dFFSR.clock_flag := ({0, 0, 0, 2, 0, 0, 0, 2, 0})[dFFREGSRL.dFFSR.clock];
[----]     elseif true then
[----]       dFFREGSRL.dFFSR.clock_flag := ({{0, 0, 0, 2, 0, 0, 0, 2, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}, {2, 2, 0, 1, 2, 2, 0, 1, 2}, {0, 0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}, {2, 2, 0, 1, 2, 2, 0, 1, 0}, {0, 0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 2, 0, 0, 0, 2, 0}})[$PRE.dFFREGSRL.dFFSR.clock, dFFREGSRL.dFFSR.clock];
[----]     end if;
[----]   end if;

[----]   dFFREGSRL.dFFSR.reset_set_flag := dFFREGSRL.dFFSR.ResetSetMap[dFFREGSRL.dFFSR.reset, dFFREGSRL.dFFSR.set];

[----]   for i in 1:2 loop
[----]     if dFFREGSRL.dFFSR.reset_set_flag == 1 then
[----]       dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 2 then
[----]       dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'1';
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 3 then
[----]       dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'0';
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 4 then
[----]       if dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 1 or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 0 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]       elseif true then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]       end if;
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 5 then
[----]       if dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'1' and ((dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'1' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'H') or dFFREGSRL.dFFSR.clock_flag == 0) then
[----]         #UNKNOWN STATEMENT#;
[----]       elseif (dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'1' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'H') and dFFREGSRL.dFFSR.clock_flag == 1 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'1';
[----]       elseif dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 1 or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 0 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]       elseif true then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]       end if;
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 6 then
[----]       dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 7 then
[----]       if dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' and ((dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'L') or dFFREGSRL.dFFSR.clock_flag == 0) then
[----]         #UNKNOWN STATEMENT#;
[----]       elseif (dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'L') and dFFREGSRL.dFFSR.clock_flag == 1 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'0';
[----]       elseif dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 1 or dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' and dFFREGSRL.dFFSR.clock_flag <> 0 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]       elseif true then
[----]         dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]       end if;
[----]     elseif dFFREGSRL.dFFSR.reset_set_flag == 8 then
[----]       if dFFREGSRL.dFFSR.clock_flag == 0 then
[----]         #UNKNOWN STATEMENT#;
[----]       elseif dFFREGSRL.dFFSR.clock_flag == 1 then
[----]         dFFREGSRL.dFFSR.nextstate[i] := ({{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}})[dFFREGSRL.dFFSR.dataIn[i], Modelica.Electrical.Digital.Interfaces.Strength.'S_X01'];
[----]       elseif true then
[----]         if dFFREGSRL.dFFSR.next_assign_val[i] == ({{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}})[dFFREGSRL.dFFSR.dataIn[i], Modelica.Electrical.Digital.Interfaces.Strength.'S_X01'] or dFFREGSRL.dFFSR.next_assign_val[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' then
[----]           #UNKNOWN STATEMENT#;
[----]         elseif dFFREGSRL.dFFSR.dataIn[i] == Modelica.Electrical.Digital.Interfaces.Logic.'U' then
[----]           dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'U';
[----]         elseif true then
[----]           dFFREGSRL.dFFSR.nextstate[i] := Modelica.Electrical.Digital.Interfaces.Logic.'X';
[----]         end if;
[----]       end if;
[----]     end if;
[----]   end for;
[----] end if;

[----] dFFREGSRL.dFFSR.next_assign_val := dFFREGSRL.dFFSR.nextstate;
[----] dFFREGSRL.dFFSR.dataOut := dFFREGSRL.dFFSR.nextstate;

         slice: {7}