Running: ./testmodel.py --libraries=/var/lib/jenkins/ws/OpenModelicaLibraryTestingWork/OpenModelica/./OMCompiler/build/lib/omlibrary/ --ompython_omhome=/usr Modelica_3.2.2_Modelica.Electrical.Digital.Examples.DLATREGSRL.conf.json
Using package ModelicaServices with version 3.2.2 (/var/lib/jenkins/ws/OpenModelicaLibraryTestingWork/OpenModelica/OMCompiler/build/lib/omlibrary/ModelicaServices 3.2.2/package.mo)
Using package Complex with version 3.2.2 (/var/lib/jenkins/ws/OpenModelicaLibraryTestingWork/OpenModelica/OMCompiler/build/lib/omlibrary/Complex 3.2.2.mo)
Using package Modelica with version 3.2.2 (/var/lib/jenkins/ws/OpenModelicaLibraryTestingWork/OpenModelica/OMCompiler/build/lib/omlibrary/Modelica 3.2.2/package.mo)
Running command: translateModel(Modelica.Electrical.Digital.Examples.DLATREGSRL,tolerance=1e-06,outputFormat="mat",numberOfIntervals=5000,variableFilter="time|dLATREGSRL.delay.inertialDelaySensitive.1..x|dLATREGSRL.delay.inertialDelaySensitive.1..y|dLATREGSRL.delay.inertialDelaySensitive.2..x|dLATREGSRL.delay.inertialDelaySensitive.2..y",fileNamePrefix="Modelica_3.2.2_Modelica.Electrical.Digital.Examples.DLATREGSRL")
Notification: Performance of loadModel(Modelica): time 2.051/2.051, allocations: 194.8 MB / 211.7 MB, free: 3.012 MB / 170.7 MB
Notification: Performance of FrontEnd - loaded program: time 0.0005452/0.0005453, allocations: 15.98 kB / 264.6 MB, free: 12.93 MB / 218.7 MB
Notification: Performance of FrontEnd - Absyn->SCode: time 0.09857/0.09915, allocations: 44.51 MB / 309.1 MB, free: 364 kB / 250.7 MB
Notification: Performance of NFInst.instantiate(Modelica.Electrical.Digital.Examples.DLATREGSRL): time 0.002455/0.1017, allocations: 1.438 MB / 310.5 MB, free: 14.91 MB / 266.7 MB
Notification: Performance of NFInst.instExpressions: time 0.003196/0.1049, allocations: 1.023 MB / 311.5 MB, free: 13.88 MB / 266.7 MB
Notification: Performance of NFInst.updateImplicitVariability: time 0.0001006/0.105, allocations: 4 kB / 311.5 MB, free: 13.87 MB / 266.7 MB
Notification: Performance of NFTyping.typeComponents: time 0.0001582/0.1052, allocations: 23.84 kB / 311.6 MB, free: 13.85 MB / 266.7 MB
Notification: Performance of NFTyping.typeBindings: time 0.0003669/0.1056, allocations: 171.6 kB / 311.7 MB, free: 13.68 MB / 266.7 MB
Notification: Performance of NFTyping.typeClassSections: time 0.0003872/0.106, allocations: 91.81 kB / 311.8 MB, free: 13.59 MB / 266.7 MB
Notification: Performance of NFFlatten.flatten: time 0.000526/0.1065, allocations: 303.5 kB / 312.1 MB, free: 13.29 MB / 266.7 MB
Notification: Performance of NFFlatten.resolveConnections: time 0.0002491/0.1068, allocations: 88.84 kB / 312.2 MB, free: 13.2 MB / 266.7 MB
Notification: Performance of NFEvalConstants.evaluate: time 0.00109/0.1079, allocations: 0.6395 MB / 312.8 MB, free: 12.56 MB / 266.7 MB
Notification: Performance of NFSimplifyModel.simplify: time 0.0003282/0.1083, allocations: 211.5 kB / 313 MB, free: 12.36 MB / 266.7 MB
Notification: Performance of NFPackage.collectConstants: time 0.0001385/0.1084, allocations: 12 kB / 313 MB, free: 12.34 MB / 266.7 MB
Notification: Performance of NFFlatten.collectFunctions: time 0.000136/0.1086, allocations: 12 kB / 313.1 MB, free: 12.33 MB / 266.7 MB
Notification: Performance of NFScalarize.scalarize: time 0.0002942/0.1089, allocations: 247.2 kB / 313.3 MB, free: 12.09 MB / 266.7 MB
Notification: Performance of NFVerifyModel.verify: time 0.00025/0.1091, allocations: 209 kB / 313.5 MB, free: 11.88 MB / 266.7 MB
Notification: Performance of NFConvertDAE.convert: time 0.001509/0.1106, allocations: 1.192 MB / 314.7 MB, free: 10.68 MB / 266.7 MB
Notification: Performance of FrontEnd - DAE generated: time 3.206e-06/0.1107, allocations: 0 / 314.7 MB, free: 10.68 MB / 266.7 MB
Notification: Performance of FrontEnd: time 2.124e-06/0.1107, allocations: 0 / 314.7 MB, free: 10.68 MB / 266.7 MB
Notification: Performance of Transformations before backend: time 1.593e-05/0.1107, allocations: 0 / 314.7 MB, free: 10.68 MB / 266.7 MB
Notification: Model statistics after passing the front-end and creating the data structures used by the back-end:
 * Number of equations: 43
 * Number of variables: 43
Notification: Performance of Generate backend data structure: time 0.002223/0.1129, allocations: 1.508 MB / 316.2 MB, free: 9.07 MB / 266.7 MB
Notification: Performance of prepare preOptimizeDAE: time 4.824e-05/0.113, allocations: 12.03 kB / 316.2 MB, free: 9.059 MB / 266.7 MB
Notification: Performance of preOpt normalInlineFunction (simulation): time 0.0002712/0.1133, allocations: 134.5 kB / 316.4 MB, free: 8.926 MB / 266.7 MB
Notification: Performance of preOpt evaluateParameters (simulation): time 0.0009484/0.1143, allocations: 0.5169 MB / 316.9 MB, free: 8.359 MB / 266.7 MB
Notification: Performance of preOpt simplifyIfEquations (simulation): time 6.497e-05/0.1143, allocations: 23.98 kB / 316.9 MB, free: 8.336 MB / 266.7 MB
Notification: Performance of preOpt expandDerOperator (simulation): time 0.0001226/0.1145, allocations: 28 kB / 316.9 MB, free: 8.309 MB / 266.7 MB
Notification: Performance of preOpt clockPartitioning (simulation): time 0.001675/0.1162, allocations: 0.6221 MB / 317.5 MB, free: 7.68 MB / 266.7 MB
Notification: Performance of preOpt findStateOrder (simulation): time 1.094e-05/0.1162, allocations: 0 / 317.5 MB, free: 7.68 MB / 266.7 MB
Notification: Performance of preOpt replaceEdgeChange (simulation): time 9.348e-05/0.1163, allocations: 16 kB / 317.6 MB, free: 7.664 MB / 266.7 MB
Notification: Performance of preOpt inlineArrayEqn (simulation): time 1.399e-05/0.1163, allocations: 7.984 kB / 317.6 MB, free: 7.656 MB / 266.7 MB
Notification: Performance of preOpt removeEqualRHS (simulation): time 0.001187/0.1175, allocations: 475.7 kB / 318 MB, free: 7.191 MB / 266.7 MB
Notification: Performance of preOpt removeSimpleEquations (simulation): time 0.002714/0.1202, allocations: 1.178 MB / 319.2 MB, free: 5.957 MB / 266.7 MB
Notification: Performance of preOpt comSubExp (simulation): time 0.001505/0.1218, allocations: 0.7092 MB / 319.9 MB, free: 5.238 MB / 266.7 MB
Notification: Performance of preOpt evalFunc (simulation): time 1.41e-05/0.1218, allocations: 0 / 319.9 MB, free: 5.238 MB / 266.7 MB
Notification: Performance of preOpt encapsulateWhenConditions (simulation): time 0.001617/0.1234, allocations: 0.7523 MB / 320.7 MB, free: 4.449 MB / 266.7 MB
Notification: Performance of pre-optimization done (n=33): time 3.677e-06/0.1235, allocations: 0 / 320.7 MB, free: 4.449 MB / 266.7 MB
Notification: Performance of matching and sorting (n=33): time 0.004853/0.1283, allocations: 2.151 MB / 322.8 MB, free: 2.188 MB / 266.7 MB
Notification: Performance of inlineWhenForInitialization (initialization): time 0.0002762/0.1287, allocations: 333 kB / 323.1 MB, free: 1.801 MB / 266.7 MB
Notification: Performance of selectInitializationVariablesDAE (initialization): time 0.004112/0.1328, allocations: 1.858 MB / 325 MB, free: 15.93 MB / 282.7 MB
Notification: Performance of collectPreVariables (initialization): time 0.000207/0.133, allocations: 45.62 kB / 325 MB, free: 15.88 MB / 282.7 MB
Notification: Performance of collectInitialEqns (initialization): time 0.0004278/0.1335, allocations: 246.4 kB / 325.3 MB, free: 15.63 MB / 282.7 MB
Notification: Performance of collectInitialBindings (initialization): time 0.0001977/0.1337, allocations: 79.09 kB / 325.4 MB, free: 15.55 MB / 282.7 MB
Notification: Performance of simplifyInitialFunctions (initialization): time 8.342e-05/0.1338, allocations: 12 kB / 325.4 MB, free: 15.54 MB / 282.7 MB
Notification: Performance of setup shared object (initialization): time 0.0002474/0.134, allocations: 374.7 kB / 325.7 MB, free: 15.16 MB / 282.7 MB
Notification: Performance of preBalanceInitialSystem (initialization): time 0.001205/0.1353, allocations: 455.8 kB / 326.2 MB, free: 14.72 MB / 282.7 MB
Notification: Performance of partitionIndependentBlocks (initialization): time 0.001169/0.1364, allocations: 498.2 kB / 326.7 MB, free: 14.22 MB / 282.7 MB
Notification: Performance of analyzeInitialSystem (initialization): time 0.001078/0.1375, allocations: 0.5871 MB / 327.3 MB, free: 13.59 MB / 282.7 MB
Notification: Performance of solveInitialSystemEqSystem (initialization): time 3.948e-06/0.1376, allocations: 0 / 327.3 MB, free: 13.59 MB / 282.7 MB
Notification: Performance of matching and sorting (n=37) (initialization): time 0.003147/0.1407, allocations: 1.377 MB / 328.6 MB, free: 12.15 MB / 282.7 MB
Notification: Performance of prepare postOptimizeDAE: time 0.0003295/0.1411, allocations: 293.5 kB / 328.9 MB, free: 11.82 MB / 282.7 MB
Notification: Performance of postOpt simplifyComplexFunction (initialization): time 9.357e-06/0.1411, allocations: 0 / 328.9 MB, free: 11.82 MB / 282.7 MB
Notification: Performance of postOpt tearingSystem (initialization): time 1.793e-05/0.1411, allocations: 4 kB / 328.9 MB, free: 11.81 MB / 282.7 MB
Notification: Performance of postOpt solveSimpleEquations (initialization): time 4.025e-05/0.1412, allocations: 4 kB / 328.9 MB, free: 11.81 MB / 282.7 MB
Notification: Performance of postOpt calculateStrongComponentJacobians (initialization): time 1.095e-05/0.1412, allocations: 12 kB / 328.9 MB, free: 11.8 MB / 282.7 MB
Notification: Performance of postOpt simplifyAllExpressions (initialization): time 0.000693/0.1419, allocations: 43.86 kB / 329 MB, free: 11.75 MB / 282.7 MB
Notification: Performance of postOpt collapseArrayExpressions (initialization): time 0.0002352/0.1422, allocations: 128.2 kB / 329.1 MB, free: 11.63 MB / 282.7 MB
Notification: Model statistics after passing the back-end for initialization:
 * Number of independent subsystems: 3
 * Number of states: 0 ()
 * Number of discrete variables: 37 ($PRE.dLATREGSRL.delay.inertialDelaySensitive[2].y,$PRE.dLATREGSRL.delay.inertialDelaySensitive[1].y,$whenCondition1,$whenCondition2,$whenCondition3,$whenCondition4,enable.y,data_0.y,reset.y,data_1.y,set.y,$PRE.dLATREGSRL.delay.inertialDelaySensitive[1].x,dLATREGSRL.delay.inertialDelaySensitive[1].x,dLATREGSRL.delay.inertialDelaySensitive[1].y,dLATREGSRL.delay.inertialDelaySensitive[1].delayTime,dLATREGSRL.delay.inertialDelaySensitive[1].y_auxiliary,dLATREGSRL.delay.inertialDelaySensitive[1].y_old,dLATREGSRL.delay.inertialDelaySensitive[1].lh,dLATREGSRL.delay.inertialDelaySensitive[1].t_next,$PRE.dLATREGSRL.delay.inertialDelaySensitive[2].x,dLATREGSRL.delay.inertialDelaySensitive[2].x,dLATREGSRL.delay.inertialDelaySensitive[2].y,dLATREGSRL.delay.inertialDelaySensitive[2].delayTime,dLATREGSRL.delay.inertialDelaySensitive[2].y_auxiliary,dLATREGSRL.delay.inertialDelaySensitive[2].y_old,dLATREGSRL.delay.inertialDelaySensitive[2].lh,dLATREGSRL.delay.inertialDelaySensitive[2].t_next,dLATREGSRL.dLATSR.dataIn[1],dLATREGSRL.dLATSR.dataIn[2],dLATREGSRL.dLATSR.dataOut[1],dLATREGSRL.dLATSR.dataOut[2],dLATREGSRL.dLATSR.enable_flag,dLATREGSRL.dLATSR.reset_set_flag,dLATREGSRL.dLATSR.nextstate[1],dLATREGSRL.dLATSR.nextstate[2],dLATREGSRL.dLATSR.next_assign_val[1],dLATREGSRL.dLATSR.next_assign_val[2])
 * Number of discrete states: 0 ()
 * Number of clocked states: 0 ()
 * Top-level inputs: 0
Notification: Strong component statistics for initialization (16):
 * Single equations (assignments): 8
 * Array equations: 0
 * Algorithm blocks: 8
 * Record equations: 0
 * When equations: 0
 * If-equations: 0
 * Equation systems (linear and non-linear blocks): 0
 * Torn equation systems: 0
 * Mixed (continuous/discrete) equation systems: 0
Notification: Performance of prepare postOptimizeDAE: time 0.001963/0.1441, allocations: 0.9958 MB / 330.1 MB, free: 10.57 MB / 282.7 MB
Notification: Performance of postOpt lateInlineFunction (simulation): time 0.0003034/0.1445, allocations: 134.4 kB / 330.2 MB, free: 10.44 MB / 282.7 MB
Notification: Performance of postOpt wrapFunctionCalls (simulation): time 0.0006066/0.1451, allocations: 251.9 kB / 330.5 MB, free: 10.2 MB / 282.7 MB
Notification: Performance of postOpt simplifysemiLinear (simulation): time 4.718e-06/0.1451, allocations: 4 kB / 330.5 MB, free: 10.19 MB / 282.7 MB
Notification: Performance of postOpt simplifyComplexFunction (simulation): time 3.387e-06/0.1451, allocations: 0 / 330.5 MB, free: 10.19 MB / 282.7 MB
Notification: Performance of postOpt removeConstants (simulation): time 0.001698/0.1468, allocations: 0.6708 MB / 331.2 MB, free: 9.5 MB / 282.7 MB
Notification: Performance of postOpt simplifyTimeIndepFuncCalls (simulation): time 0.0003292/0.1472, allocations: 63.95 kB / 331.2 MB, free: 9.438 MB / 282.7 MB
Notification: Performance of postOpt simplifyAllExpressions (simulation): time 0.0005486/0.1477, allocations: 35.97 kB / 331.3 MB, free: 9.402 MB / 282.7 MB
Notification: Performance of postOpt findZeroCrossings (simulation): time 0.0009718/0.1487, allocations: 375.6 kB / 331.6 MB, free: 9.035 MB / 282.7 MB
Notification: Performance of postOpt createDAEmodeBDAE (simulation): time 0.003761/0.1525, allocations: 2.032 MB / 333.7 MB, free: 6.848 MB / 282.7 MB
Notification: Performance of postOpt detectDAEmodeSparsePattern (simulation): time 0.003687/0.1562, allocations: 1.747 MB / 335.4 MB, free: 5.031 MB / 282.7 MB
Notification: Performance of postOpt setEvaluationStage (simulation): time 0.001722/0.158, allocations: 0.9333 MB / 336.3 MB, free: 4.098 MB / 282.7 MB
Notification: Performance of sorting global known variables: time 0.00453/0.1625, allocations: 1.345 MB / 337.7 MB, free: 2.75 MB / 282.7 MB
Notification: Performance of Backend: time 1.624e-06/0.1626, allocations: 7.938 kB / 337.7 MB, free: 2.742 MB / 282.7 MB
Notification: Performance of simCode: created initialization part: time 0.004869/0.1675, allocations: 1.529 MB / 339.2 MB, free: 1.105 MB / 282.7 MB
Notification: Performance of SimCode: time 0.01045/0.178, allocations: 3.595 MB / 342.8 MB, free: 13.36 MB / 298.7 MB
Notification: Performance of Templates: time 0.04618/0.2243, allocations: 13.6 MB / 356.4 MB, free: 15.43 MB / 314.7 MB
""

Variables in the reference:time,dLATREGSRL.delay.inertialDelaySensitive[1].x,dLATREGSRL.delay.inertialDelaySensitive[1].y,dLATREGSRL.delay.inertialDelaySensitive[2].x,dLATREGSRL.delay.inertialDelaySensitive[2].y

Variables in the result:dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dLATREGSRL.dLATSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dLATREGSRL.dLATSR.n,dLATREGSRL.dLATSR.strength,dLATREGSRL.delay.inertialDelaySensitive[1].tHL,dLATREGSRL.delay.inertialDelaySensitive[1].tLH,dLATREGSRL.delay.inertialDelaySensitive[1].x,dLATREGSRL.delay.inertialDelaySensitive[1].y,dLATREGSRL.delay.inertialDelaySensitive[1].y0,dLATREGSRL.delay.inertialDelaySensitive[2].tHL,dLATREGSRL.delay.inertialDelaySensitive[2].tLH,dLATREGSRL.delay.inertialDelaySensitive[2].x,dLATREGSRL.delay.inertialDelaySensitive[2].y,dLATREGSRL.delay.inertialDelaySensitive[2].y0,dLATREGSRL.delay.n,dLATREGSRL.delay.tHL,dLATREGSRL.delay.tLH,dLATREGSRL.n,dLATREGSRL.strength,dLATREGSRL.tHL,dLATREGSRL.tLH,data_0.n,data_0.t[1],data_0.t[2],data_0.x[1],data_0.x[2],data_0.y0,data_1.n,data_1.t[1],data_1.t[2],data_1.x[1],data_1.x[2],data_1.y0,enable.n,enable.t[1],enable.t[2],enable.t[3],enable.x[1],enable.x[2],enable.x[3],enable.y0,reset.n,reset.t[1],reset.t[2],reset.t[3],reset.t[4],reset.t[5],reset.x[1],reset.x[2],reset.x[3],reset.x[4],reset.x[5],reset.y0,set.n,set.t[1],set.t[2],set.t[3],set.x[1],set.x[2],set.x[3],set.y0,time