Notification: Performance of loadModel(Modelica_Synchronous): time 1.596/1.596, allocations: 207.2 MB / 213.5 MB, free: 8.875 MB / 184.6 MB
Notification: Performance of FrontEnd - loaded program: time 0.1804/1.777, allocations: 49.14 MB / 262.6 MB, free: 7.543 MB / 216.6 MB
Notification: Performance of FrontEnd - Absyn->SCode: time 0.06994/1.847, allocations: 47.15 MB / 309.8 MB, free: 8.285 MB / 264.6 MB
[Modelica_Synchronous 0.92.1/WorkInProgress.mo:1599:7-1602:72:writable] Error: Class Modelica_LinearSystems2.Controller.SampleClock not found in scope Modelica_Synchronous.WorkInProgress.Tests.TestFIR_Step2.
Error: Error occurred while flattening model Modelica_Synchronous.WorkInProgress.Tests.TestFIR_Step2
Error: Internal error SimCode: The model Modelica_Synchronous.WorkInProgress.Tests.TestFIR_Step2 could not be translated to FMU