Notification: Performance of loadModel(Modelica_Synchronous): time 1.619/1.619, allocations: 207.2 MB / 213.5 MB, free: 8.867 MB / 184.6 MB
Notification: Performance of FrontEnd - loaded program: time 0.2121/1.831, allocations: 49.12 MB / 262.6 MB, free: 7.547 MB / 216.6 MB
Notification: Performance of FrontEnd - Absyn->SCode: time 0.1045/1.936, allocations: 47.17 MB / 309.8 MB, free: 8.289 MB / 264.6 MB
[Modelica_Synchronous 0.92.1/WorkInProgress.mo:1530:7-1533:75:writable] Error: Class Modelica_LinearSystems2.Controller.SampleClock not found in scope Modelica_Synchronous.WorkInProgress.Tests.TestFIR_Step.
Error: Error occurred while flattening model Modelica_Synchronous.WorkInProgress.Tests.TestFIR_Step
Error: Internal error SimCode: The model Modelica_Synchronous.WorkInProgress.Tests.TestFIR_Step could not be translated to FMU