Running command: "" <> buildModelFMU(Modelica.Electrical.Digital.Examples.DFFREGSRL,fileNamePrefix="Modelica_3_2_2_cs_Modelica_Electrical_Digital_Examples_DFFREGSRL",fmuType="cs",version="2.0",platforms={"dynamic"})
Notification: Performance of loadModel(Modelica): time 2.456/2.456, allocations: 195 MB / 202.9 MB, free: 6.727 MB / 170.7 MB
Notification: Performance of FrontEnd - loaded program: time 2.609e-05/2.628e-05, allocations: 4.688 kB / 249.8 MB, free: 5.234 MB / 202.7 MB
Notification: Performance of FrontEnd - Absyn->SCode: time 0.1003/0.1003, allocations: 44.51 MB / 294.3 MB, free: 10.66 MB / 250.7 MB
Notification: Performance of FrontEnd - scodeFlatten: time 0.5179/0.6182, allocations: 77.5 MB / 371.8 MB, free: 7.199 MB / 298.7 MB
Notification: Performance of FrontEnd - mkProgramGraph: time 0.0003874/0.6187, allocations: 67.62 kB / 371.8 MB, free: 7.199 MB / 298.7 MB
Notification: Performance of FrontEnd - DAE generated: time 0.1344/0.7532, allocations: 32.57 MB / 404.4 MB, free: 12.63 MB / 314.7 MB
Notification: Performance of FrontEnd: time 3.026e-06/0.7532, allocations: 0 / 404.4 MB, free: 12.63 MB / 314.7 MB
Notification: Performance of Transformations before backend: time 6.89e-05/0.7533, allocations: 22.78 kB / 404.4 MB, free: 12.63 MB / 314.7 MB
Notification: Model statistics after passing the front-end and creating the data structures used by the back-end:
 * Number of equations: 43
 * Number of variables: 43
Notification: Performance of Generate backend data structure: time 0.002597/0.7559, allocations: 1.294 MB / 405.7 MB, free: 11.56 MB / 314.7 MB
Notification: Performance of prepare preOptimizeDAE: time 6.408e-05/0.756, allocations: 11.55 kB / 405.7 MB, free: 11.56 MB / 314.7 MB
Notification: Performance of preOpt introduceOutputAliases (simulation): time 0.000261/0.7563, allocations: 63.17 kB / 405.8 MB, free: 11.51 MB / 314.7 MB
Notification: Performance of preOpt normalInlineFunction (simulation): time 0.0003718/0.7567, allocations: 132.4 kB / 405.9 MB, free: 11.45 MB / 314.7 MB
Notification: Performance of preOpt evaluateParameters (simulation): time 0.001477/0.7582, allocations: 0.5103 MB / 406.4 MB, free: 11.1 MB / 314.7 MB
Notification: Performance of preOpt simplifyIfEquations (simulation): time 7.542e-05/0.7583, allocations: 22.59 kB / 406.4 MB, free: 11.09 MB / 314.7 MB
Notification: Performance of preOpt expandDerOperator (simulation): time 0.0001726/0.7585, allocations: 27.27 kB / 406.5 MB, free: 11.09 MB / 314.7 MB
Notification: Performance of preOpt removeEqualFunctionCalls (simulation): time 0.001247/0.7597, allocations: 444.4 kB / 406.9 MB, free: 11.03 MB / 314.7 MB
Notification: Performance of preOpt clockPartitioning (simulation): time 0.00178/0.7615, allocations: 0.5901 MB / 407.5 MB, free: 10.75 MB / 314.7 MB
Notification: Performance of preOpt findStateOrder (simulation): time 2.149e-05/0.7616, allocations: 7.984 kB / 407.5 MB, free: 10.74 MB / 314.7 MB
Notification: Performance of preOpt replaceEdgeChange (simulation): time 0.0001403/0.7617, allocations: 9.812 kB / 407.5 MB, free: 10.73 MB / 314.7 MB
Notification: Performance of preOpt inlineArrayEqn (simulation): time 1.227e-05/0.7618, allocations: 4 kB / 407.5 MB, free: 10.73 MB / 314.7 MB
Notification: Performance of preOpt removeSimpleEquations (simulation): time 0.003438/0.7652, allocations: 1.047 MB / 408.6 MB, free: 9.863 MB / 314.7 MB
Notification: Performance of preOpt comSubExp (simulation): time 0.001781/0.7671, allocations: 0.6704 MB / 409.2 MB, free: 9.48 MB / 314.7 MB
Notification: Performance of preOpt resolveLoops (simulation): time 0.001614/0.7687, allocations: 0.6568 MB / 409.9 MB, free: 9.117 MB / 314.7 MB
Notification: Performance of preOpt evalFunc (simulation): time 2.046e-05/0.7688, allocations: 0 / 409.9 MB, free: 9.117 MB / 314.7 MB
Notification: Performance of preOpt encapsulateWhenConditions (simulation): time 0.002089/0.7709, allocations: 0.7744 MB / 410.7 MB, free: 8.465 MB / 314.7 MB
Notification: Performance of pre-optimization done (n=36): time 4.308e-06/0.7709, allocations: 0 / 410.7 MB, free: 8.465 MB / 314.7 MB
Notification: Performance of matching and sorting (n=36): time 0.003834/0.7748, allocations: 1.089 MB / 411.8 MB, free: 7.617 MB / 314.7 MB
Notification: Performance of inlineWhenForInitialization (initialization): time 0.0003579/0.7752, allocations: 327.8 kB / 412.1 MB, free: 7.254 MB / 314.7 MB
Notification: Performance of selectInitializationVariablesDAE (initialization): time 0.005053/0.7803, allocations: 1.537 MB / 413.6 MB, free: 5.98 MB / 314.7 MB
Notification: Performance of collectPreVariables (initialization): time 0.0003117/0.7806, allocations: 45.25 kB / 413.7 MB, free: 5.934 MB / 314.7 MB
Notification: Performance of collectInitialEqns (initialization): time 0.0005172/0.7812, allocations: 243.4 kB / 413.9 MB, free: 5.781 MB / 314.7 MB
Notification: Performance of collectInitialBindings (initialization): time 0.0003033/0.7815, allocations: 77.8 kB / 414 MB, free: 5.715 MB / 314.7 MB
Notification: Performance of simplifyInitialFunctions (initialization): time 0.0001319/0.7816, allocations: 15.36 kB / 414 MB, free: 5.703 MB / 314.7 MB
Notification: Performance of setup shared object (initialization): time 0.0003018/0.7819, allocations: 382.1 kB / 414.4 MB, free: 5.344 MB / 314.7 MB
Notification: Performance of preBalanceInitialSystem (initialization): time 0.001391/0.7834, allocations: 437.2 kB / 414.8 MB, free: 5.051 MB / 314.7 MB
Notification: Performance of partitionIndependentBlocks (initialization): time 0.001362/0.7848, allocations: 434 kB / 415.2 MB, free: 4.766 MB / 314.7 MB
Notification: Performance of analyzeInitialSystem (initialization): time 0.000927/0.7857, allocations: 286.4 kB / 415.5 MB, free: 4.574 MB / 314.7 MB
Notification: Performance of solveInitialSystemEqSystem (initialization): time 5.491e-06/0.7858, allocations: 4 kB / 415.5 MB, free: 4.57 MB / 314.7 MB
Notification: Performance of matching and sorting (n=43) (initialization): time 0.003722/0.7895, allocations: 1.033 MB / 416.5 MB, free: 3.789 MB / 314.7 MB
Notification: Performance of prepare postOptimizeDAE: time 0.0004268/0.79, allocations: 298.2 kB / 416.8 MB, free: 3.473 MB / 314.7 MB
Notification: Performance of postOpt simplifyComplexFunction (initialization): time 1.039e-05/0.79, allocations: 0 / 416.8 MB, free: 3.473 MB / 314.7 MB
Notification: Performance of postOpt tearingSystem (initialization): time 2.797e-05/0.7901, allocations: 0 / 416.8 MB, free: 3.473 MB / 314.7 MB
Notification: Performance of postOpt solveSimpleEquations (initialization): time 5.789e-05/0.7901, allocations: 7.984 kB / 416.8 MB, free: 3.465 MB / 314.7 MB
Notification: Performance of postOpt calculateStrongComponentJacobians (initialization): time 7.133e-06/0.7901, allocations: 0 / 416.8 MB, free: 3.465 MB / 314.7 MB
Notification: Performance of postOpt simplifyAllExpressions (initialization): time 0.0009414/0.7911, allocations: 43.95 kB / 416.9 MB, free: 3.422 MB / 314.7 MB
Notification: Performance of postOpt collapseArrayExpressions (initialization): time 0.0003999/0.7915, allocations: 152.5 kB / 417 MB, free: 3.277 MB / 314.7 MB
Notification: Model statistics after passing the back-end for initialization:
 * Number of independent subsystems: 1
 * Number of states: 0 ()
 * Number of discrete variables: 43 ($whenCondition1,$whenCondition2,$whenCondition3,$whenCondition4,clock.y,data_0.y,reset.y,data_1.y,set.y,$PRE.dFFREGSRL.delay.inertialDelaySensitive[1].x,dFFREGSRL.delay.inertialDelaySensitive[1].x,$PRE.dFFREGSRL.delay.inertialDelaySensitive[1].y,dFFREGSRL.delay.inertialDelaySensitive[1].y,dFFREGSRL.delay.inertialDelaySensitive[1].delayTime,dFFREGSRL.delay.inertialDelaySensitive[1].y_auxiliary,dFFREGSRL.delay.inertialDelaySensitive[1].y_old,dFFREGSRL.delay.inertialDelaySensitive[1].lh,dFFREGSRL.delay.inertialDelaySensitive[1].t_next,$PRE.dFFREGSRL.delay.inertialDelaySensitive[2].x,dFFREGSRL.delay.inertialDelaySensitive[2].x,$PRE.dFFREGSRL.delay.inertialDelaySensitive[2].y,dFFREGSRL.delay.inertialDelaySensitive[2].y,dFFREGSRL.delay.inertialDelaySensitive[2].delayTime,dFFREGSRL.delay.inertialDelaySensitive[2].y_auxiliary,dFFREGSRL.delay.inertialDelaySensitive[2].y_old,dFFREGSRL.delay.inertialDelaySensitive[2].lh,dFFREGSRL.delay.inertialDelaySensitive[2].t_next,$PRE.dFFREGSRL.dFFSR.set,dFFREGSRL.dFFSR.set,$PRE.dFFREGSRL.dFFSR.reset,dFFREGSRL.dFFSR.reset,$PRE.dFFREGSRL.dFFSR.clock,dFFREGSRL.dFFSR.clock,dFFREGSRL.dFFSR.dataIn[1],dFFREGSRL.dFFSR.dataIn[2],dFFREGSRL.dFFSR.dataOut[1],dFFREGSRL.dFFSR.dataOut[2],dFFREGSRL.dFFSR.clock_flag,dFFREGSRL.dFFSR.reset_set_flag,dFFREGSRL.dFFSR.nextstate[1],dFFREGSRL.dFFSR.nextstate[2],dFFREGSRL.dFFSR.next_assign_val[1],dFFREGSRL.dFFSR.next_assign_val[2])
 * Number of discrete states: 0 ()
 * Top-level inputs: 0
Notification: Strong component statistics for initialization (22):
 * Single equations (assignments): 14
 * Array equations: 0
 * Algorithm blocks: 8
 * Record equations: 0
 * When equations: 0
 * If-equations: 0
 * Equation systems (linear and non-linear blocks): 0
 * Torn equation systems: 0
 * Mixed (continuous/discrete) equation systems: 0
Notification: Performance of prepare postOptimizeDAE: time 0.0008704/0.7924, allocations: 478.2 kB / 417.5 MB, free: 2.785 MB / 314.7 MB
Notification: Performance of postOpt lateInlineFunction (simulation): time 0.0004019/0.7928, allocations: 130.5 kB / 417.6 MB, free: 2.656 MB / 314.7 MB
Notification: Performance of postOpt wrapFunctionCalls (simulation): time 0.001061/0.7939, allocations: 248.6 kB / 417.9 MB, free: 2.434 MB / 314.7 MB
Notification: Performance of postOpt inlineArrayEqn (simulation): time 6.612e-06/0.7939, allocations: 0 / 417.9 MB, free: 2.434 MB / 314.7 MB
Notification: Performance of postOpt constantLinearSystem (simulation): time 7.744e-06/0.794, allocations: 0 / 417.9 MB, free: 2.434 MB / 314.7 MB
Notification: Performance of postOpt simplifysemiLinear (simulation): time 1.086e-05/0.794, allocations: 3.984 kB / 417.9 MB, free: 2.43 MB / 314.7 MB
Notification: Performance of postOpt removeSimpleEquations (simulation): time 0.006326/0.8003, allocations: 2.004 MB / 419.9 MB, free: 0.6797 MB / 314.7 MB
Notification: Performance of postOpt simplifyComplexFunction (simulation): time 1.294e-05/0.8004, allocations: 3.984 kB / 419.9 MB, free: 0.6758 MB / 314.7 MB
Notification: Performance of postOpt solveSimpleEquations (simulation): time 3.557e-05/0.8004, allocations: 8 kB / 419.9 MB, free: 0.668 MB / 314.7 MB
Notification: Performance of postOpt tearingSystem (simulation): time 9.278e-06/0.8005, allocations: 0 / 419.9 MB, free: 0.668 MB / 314.7 MB
Notification: Performance of postOpt inputDerivativesUsed (simulation): time 0.0001898/0.8007, allocations: 39.73 kB / 419.9 MB, free: 0.6328 MB / 314.7 MB
Notification: Performance of postOpt calculateStrongComponentJacobians (simulation): time 4.799e-06/0.8007, allocations: 3.938 kB / 419.9 MB, free: 0.6289 MB / 314.7 MB
Notification: Performance of postOpt calculateStateSetsJacobians (simulation): time 4.328e-06/0.8007, allocations: 0 / 419.9 MB, free: 0.6289 MB / 314.7 MB
Notification: Performance of postOpt symbolicJacobian (simulation): time 0.004112/0.8048, allocations: 1.277 MB / 421.2 MB, free: 15.33 MB / 330.7 MB
Notification: Performance of postOpt removeConstants (simulation): time 0.002569/0.8074, allocations: 0.6747 MB / 421.9 MB, free: 14.63 MB / 330.7 MB
Notification: Performance of postOpt simplifyTimeIndepFuncCalls (simulation): time 0.0004175/0.8079, allocations: 55.97 kB / 421.9 MB, free: 14.58 MB / 330.7 MB
Notification: Performance of postOpt simplifyAllExpressions (simulation): time 0.0008801/0.8088, allocations: 47.86 kB / 422 MB, free: 14.53 MB / 330.7 MB
Notification: Performance of postOpt findZeroCrossings (simulation): time 0.00134/0.8101, allocations: 347.7 kB / 422.3 MB, free: 14.19 MB / 330.7 MB
Notification: Performance of postOpt collapseArrayExpressions (simulation): time 0.0004093/0.8106, allocations: 159.9 kB / 422.5 MB, free: 14.04 MB / 330.7 MB
Notification: Performance of sorting global known variables: time 0.004177/0.8148, allocations: 1.255 MB / 423.7 MB, free: 12.78 MB / 330.7 MB
Notification: Performance of sort global known variables: time 1.042e-06/0.8148, allocations: 0 / 423.7 MB, free: 12.78 MB / 330.7 MB
Notification: Performance of remove unused functions: time 0.001256/0.8161, allocations: 152 kB / 423.9 MB, free: 12.63 MB / 330.7 MB
Notification: Model statistics after passing the back-end for simulation:
 * Number of independent subsystems: 1
 * Number of states: 0 ()
 * Number of discrete variables: 36 ($whenCondition1,$whenCondition2,$whenCondition3,$whenCondition4,clock.y,data_0.y,reset.y,data_1.y,set.y,dFFREGSRL.delay.inertialDelaySensitive[1].x,dFFREGSRL.delay.inertialDelaySensitive[1].y,dFFREGSRL.delay.inertialDelaySensitive[1].delayTime,dFFREGSRL.delay.inertialDelaySensitive[1].y_auxiliary,dFFREGSRL.delay.inertialDelaySensitive[1].y_old,dFFREGSRL.delay.inertialDelaySensitive[1].lh,dFFREGSRL.delay.inertialDelaySensitive[1].t_next,dFFREGSRL.delay.inertialDelaySensitive[2].x,dFFREGSRL.delay.inertialDelaySensitive[2].y,dFFREGSRL.delay.inertialDelaySensitive[2].delayTime,dFFREGSRL.delay.inertialDelaySensitive[2].y_auxiliary,dFFREGSRL.delay.inertialDelaySensitive[2].y_old,dFFREGSRL.delay.inertialDelaySensitive[2].lh,dFFREGSRL.delay.inertialDelaySensitive[2].t_next,dFFREGSRL.dFFSR.set,dFFREGSRL.dFFSR.reset,dFFREGSRL.dFFSR.clock,dFFREGSRL.dFFSR.dataIn[1],dFFREGSRL.dFFSR.dataIn[2],dFFREGSRL.dFFSR.dataOut[1],dFFREGSRL.dFFSR.dataOut[2],dFFREGSRL.dFFSR.clock_flag,dFFREGSRL.dFFSR.reset_set_flag,dFFREGSRL.dFFSR.nextstate[1],dFFREGSRL.dFFSR.nextstate[2],dFFREGSRL.dFFSR.next_assign_val[1],dFFREGSRL.dFFSR.next_assign_val[2])
 * Number of discrete states: 34 (set.y,data_1.y,reset.y,data_0.y,clock.y,dFFREGSRL.dFFSR.dataOut[2],dFFREGSRL.dFFSR.dataOut[1],dFFREGSRL.dFFSR.next_assign_val[2],dFFREGSRL.dFFSR.next_assign_val[1],dFFREGSRL.dFFSR.nextstate[2],dFFREGSRL.dFFSR.nextstate[1],dFFREGSRL.dFFSR.reset_set_flag,dFFREGSRL.dFFSR.clock_flag,dFFREGSRL.dFFSR.clock,dFFREGSRL.dFFSR.reset,dFFREGSRL.dFFSR.set,dFFREGSRL.delay.inertialDelaySensitive[2].y,dFFREGSRL.delay.inertialDelaySensitive[2].y_auxiliary,dFFREGSRL.delay.inertialDelaySensitive[2].t_next,dFFREGSRL.delay.inertialDelaySensitive[2].delayTime,dFFREGSRL.delay.inertialDelaySensitive[2].lh,dFFREGSRL.delay.inertialDelaySensitive[2].y_old,$whenCondition4,$whenCondition3,dFFREGSRL.delay.inertialDelaySensitive[2].x,dFFREGSRL.delay.inertialDelaySensitive[1].y,dFFREGSRL.delay.inertialDelaySensitive[1].y_auxiliary,dFFREGSRL.delay.inertialDelaySensitive[1].t_next,dFFREGSRL.delay.inertialDelaySensitive[1].delayTime,dFFREGSRL.delay.inertialDelaySensitive[1].lh,dFFREGSRL.delay.inertialDelaySensitive[1].y_old,$whenCondition2,$whenCondition1,dFFREGSRL.delay.inertialDelaySensitive[1].x)
 * Top-level inputs: 0
Notification: Strong component statistics for simulation (15):
 * Single equations (assignments): 7
 * Array equations: 0
 * Algorithm blocks: 8
 * Record equations: 0
 * When equations: 0
 * If-equations: 0
 * Equation systems (linear and non-linear blocks): 0
 * Torn equation systems: 0
 * Mixed (continuous/discrete) equation systems: 0
Notification: Performance of Backend phase and start with SimCode phase: time 0.004919/0.821, allocations: 1.923 MB / 425.8 MB, free: 10.68 MB / 330.7 MB
Notification: Performance of simCode: created initialization part: time 0.004692/0.8258, allocations: 1.862 MB / 427.7 MB, free: 8.715 MB / 330.7 MB
Notification: Performance of simCode: created event and clocks part: time 5.841e-06/0.8259, allocations: 4 kB / 427.7 MB, free: 8.711 MB / 330.7 MB
Notification: Performance of simCode: created simulation system equations: time 0.00282/0.8287, allocations: 1.374 MB / 429 MB, free: 7.238 MB / 330.7 MB
Notification: Performance of simCode: created of all other equations (e.g. parameter, nominal, assert, etc): time 0.002868/0.8317, allocations: 299.7 kB / 429.3 MB, free: 6.949 MB / 330.7 MB
Notification: Performance of simCode: created linear, non-linear and system jacobian parts: time 0.01002/0.8417, allocations: 2.675 MB / 432 MB, free: 4.219 MB / 330.7 MB
Notification: Performance of simCode: some other stuff during SimCode phase: time 0.002166/0.8439, allocations: 1.228 MB / 433.2 MB, free: 2.961 MB / 330.7 MB
Notification: Performance of simCode: alias equations: time 0.0006433/0.8446, allocations: 151 kB / 433.4 MB, free: 2.812 MB / 330.7 MB
Notification: Performance of simCode: all other stuff during SimCode phase: time 0.0003676/0.845, allocations: 151.4 kB / 433.5 MB, free: 2.664 MB / 330.7 MB
Notification: Performance of SimCode: time 1.422e-06/0.845, allocations: 0 / 433.5 MB, free: 2.664 MB / 330.7 MB
Notification: Performance of buildModelFMU: Generate the FMI files: time 0.1244/0.9694, allocations: 21.87 MB / 455.4 MB, free: 12.44 MB / 362.7 MB
Notification: Performance of buildModelFMU: configured platform dynamic using cached values: time 0.0004035/0.9699, allocations: 137.4 kB / 455.5 MB, free: 12.25 MB / 362.7 MB
Notification: Performance of buildModelFMU: Generate platform dynamic: time 4.04/5.01, allocations: 0 / 455.5 MB, free: 12.25 MB / 362.7 MB
""

Variables in the reference:time,dFFREGSRL.dataOut[1],dFFREGSRL.dataOut[2]

Variables in the result:_D_whenCondition1,_D_whenCondition2,_D_whenCondition3,_D_whenCondition4,clock.n,clock.t[1],clock.t[2],clock.t[3],clock.x[1],clock.x[2],clock.x[3],clock.y,clock.y0,dFFREGSRL.clock,dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'-',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'0',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'1',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'H',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'L',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'U',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'W',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'X',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'-'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'0'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'1'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'H'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'L'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'U'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'W'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'X'],dFFREGSRL.dFFSR.ResetSetMap[Modelica.Electrical.Digital.Interfaces.Logic.'Z',Modelica.Electrical.Digital.Interfaces.Logic.'Z'],dFFREGSRL.dFFSR.clock,dFFREGSRL.dFFSR.clock_flag,dFFREGSRL.dFFSR.dataIn[1],dFFREGSRL.dFFSR.dataIn[2],dFFREGSRL.dFFSR.dataOut[1],dFFREGSRL.dFFSR.dataOut[2],dFFREGSRL.dFFSR.n,dFFREGSRL.dFFSR.next_assign_val[1],dFFREGSRL.dFFSR.next_assign_val[2],dFFREGSRL.dFFSR.nextstate[1],dFFREGSRL.dFFSR.nextstate[2],dFFREGSRL.dFFSR.reset,dFFREGSRL.dFFSR.reset_set_flag,dFFREGSRL.dFFSR.set,dFFREGSRL.dFFSR.strength,dFFREGSRL.dataIn[1],dFFREGSRL.dataIn[2],dFFREGSRL.dataOut[1],dFFREGSRL.dataOut[2],dFFREGSRL.delay.inertialDelaySensitive[1].delayTime,dFFREGSRL.delay.inertialDelaySensitive[1].lh,dFFREGSRL.delay.inertialDelaySensitive[1].tHL,dFFREGSRL.delay.inertialDelaySensitive[1].tLH,dFFREGSRL.delay.inertialDelaySensitive[1].t_next,dFFREGSRL.delay.inertialDelaySensitive[1].x,dFFREGSRL.delay.inertialDelaySensitive[1].y,dFFREGSRL.delay.inertialDelaySensitive[1].y0,dFFREGSRL.delay.inertialDelaySensitive[1].y_auxiliary,dFFREGSRL.delay.inertialDelaySensitive[1].y_old,dFFREGSRL.delay.inertialDelaySensitive[2].delayTime,dFFREGSRL.delay.inertialDelaySensitive[2].lh,dFFREGSRL.delay.inertialDelaySensitive[2].tHL,dFFREGSRL.delay.inertialDelaySensitive[2].tLH,dFFREGSRL.delay.inertialDelaySensitive[2].t_next,dFFREGSRL.delay.inertialDelaySensitive[2].x,dFFREGSRL.delay.inertialDelaySensitive[2].y,dFFREGSRL.delay.inertialDelaySensitive[2].y0,dFFREGSRL.delay.inertialDelaySensitive[2].y_auxiliary,dFFREGSRL.delay.inertialDelaySensitive[2].y_old,dFFREGSRL.delay.n,dFFREGSRL.delay.tHL,dFFREGSRL.delay.tLH,dFFREGSRL.delay.x[1],dFFREGSRL.delay.x[2],dFFREGSRL.delay.y[1],dFFREGSRL.delay.y[2],dFFREGSRL.n,dFFREGSRL.reset,dFFREGSRL.set,dFFREGSRL.strength,dFFREGSRL.tHL,dFFREGSRL.tLH,data_0.n,data_0.t[1],data_0.x[1],data_0.y,data_0.y0,data_1.n,data_1.t[1],data_1.x[1],data_1.y,data_1.y0,reset.n,reset.t[1],reset.t[2],reset.t[3],reset.x[1],reset.x[2],reset.x[3],reset.y,reset.y0,set.n,set.t[1],set.t[2],set.t[3],set.x[1],set.x[2],set.x[3],set.y,set.y0,time