OpenModelica v1.24-fmi-fmpy from 2025-06-30 16:31:33 to 2025-07-06 07:22:30

Summary

OMC Commits0
Libraries Changed1
Number of Improvements30
Number of Regressions0
Number of Performance Improvements0
Number of Performance Regressions0

OpenModelica Changes

CommitDateAuthorSummary

OpenModelicaLibraryTesting Changes

CommitDateAuthorSummary
ed227ef2025-06-28 00:10:54 +0200Francesco CasellaRead for new round of testing June 2025 (#215)
6d6bfe52025-05-29 01:41:14 +0200Adrian PopAdd new json field to force library version exact match - to be used for MSL (#213)

Library Changes

LibraryChange
DynawoFrom version 1.6.0 (cc53d0b0949acbcfb32f28e708746ec0ce03958c) usage: __main__.py [-h] [--version] [--validate] [--start-time START_TIME] FMPy version: 0.3.21 Python version: 3.10.12 (main, May 27 2025, 17:12:29) [GCC 11.4.0] --version show program's version number and exit to 1.6.1 (c6d66d4e9ab03183044bf724efd4af657ded9315) usage: __main__.py [-h] [--version] [--validate] [--start-time START_TIME] FMPy version: 0.3.21 Python version: 3.10.12 (main, May 27 2025, 17:12:29) [GCC 11.4.0] --version show program's version number and exit

Models Affected

DynawoDynawo.Examples.DynaFlow.IEEE14.TestCases.IEEE14DisconnectLine (sim)Failed → FrontEnd
DynawoDynawo.Examples.DynaFlow.IEEE14.TestCases.IEEE14NoEvent (sim)Failed → FrontEnd
DynawoDynawo.Examples.DynaFlow.IllustrativeExamples.CoordinatedVControl (sim)Failed → FrontEnd
DynawoDynawo.Examples.HVDC.HVDC (sim)Failed → Simulate
DynawoDynawo.Examples.Nordic.TestCases.LoadFlow (sim)Failed → SimCode
DynawoDynawo.Examples.Nordic.TestCases.TestCase (sim)Failed → FrontEnd
DynawoDynawo.Examples.RVS.TestCases.LoadFlow (sim)Failed → FrontEnd
DynawoDynawo.Examples.RVS.TestCases.TestA.TestAAlphaBetaLoadNoRestorative (sim)Failed → FrontEnd
DynawoDynawo.Examples.RVS.TestCases.TestA.TestAAlphaBetaLoadRestorative (sim)Failed → FrontEnd
DynawoDynawo.Examples.RVS.TestCases.TestA.TestAShuntNoRestorative (sim)Failed → FrontEnd
DynawoDynawo.Examples.RVS.TestCases.TestB.TestBNoSvcLoadReset (sim)Failed → FrontEnd
DynawoDynawo.Examples.RVS.TestCases.TestB.TestBNoSvcNoLoadReset (sim)Failed → FrontEnd
DynawoDynawo.Examples.RVS.TestCases.TestB.TestBSvcLoadReset (sim)Failed → FrontEnd
DynawoDynawo.Examples.RVS.TestCases.TestB.TestBSvcNoLoadReset (sim)Failed → FrontEnd
DynawoDynawo.Examples.SMIB.SMIBStepEfdPm (sim)Failed → SimCode
DynawoDynawo.Examples.SMIB.SMIBStepPm (sim)Failed → Simulate
DynawoDynawo.Examples.SMIB.Standard.GovSteam1ExcIEEEST4BPssIEEE2B1 (sim)Failed → Simulate
DynawoDynawo.Examples.SMIB.Standard.GovSteam1ExcIEEEST4BPssIEEE2B2 (sim)Failed → Simulate
DynawoDynawo.Examples.SMIB.Standard.GovSteam1ExcIEEEST4BPssIEEE2B3 (sim)Failed → Simulate
DynawoDynawo.Examples.SVarC.SVarCFaultImp (sim)Failed → FrontEnd
DynawoDynawo.Examples.SVarC.SVarCLoadVarQ (sim)Failed → FrontEnd
DynawoDynawo.Examples.SVarC.SVarCLoadVarQLarge (sim)Failed → FrontEnd
DynawoDynawo.Examples.SVarC.SVarCModeChange (sim)Failed → FrontEnd
DynawoDynawo.Examples.SVarC.SVarCStepURef (sim)Failed → FrontEnd
DynawoDynawo.Examples.Wind.IEC.Neplan.WT4ACurrentSource (sim)Failed → SimCode
DynawoDynawo.Examples.Wind.IEC.Neplan.WT4ACurrentSourceFOCB (sim)Failed → SimCode
DynawoDynawo.Examples.Wind.IEC.Neplan.WT4BCurrentSource (sim)Failed → SimCode
DynawoDynawo.Examples.Wind.IEC.Neplan.WT4BCurrentSourceFOCB (sim)Failed → SimCode
DynawoDynawo.Examples.Wind.WECC.WT4ACurrentSource (sim)Failed → Simulate
DynawoDynawo.Examples.Wind.WECC.WT4BCurrentSource (sim)Failed → Simulate